Wikipedia menziona questo articolo senza entrare nei dettagli: L'architettura del processore Intel 80x86: insidie per i sistemi sicuri :
As mentioned in the preceding scenario, caches present potential for covert timing channels. Even without MSRs for direct measurements of cache activity, cache hits and misses can be detected strictly from instruction timing, as described in Wray1991. To eliminate these flows, caches must be managed. This can reduce their efficiency considerably, depending on cache architecture, as it introduces otherwise unnecessary cache flush and invalidation activity.
Wray1991 è
John C Wray: An analysis of Covert Timing Channels, Proceedings of the IEEE Computer Society Symposium on Research in Security and Privacy, Oakland, CA, pages 2-7, 1991.
Sembra abbastanza vicino a Meltdown / Spectre, vero?